[{"data":1,"prerenderedAt":83},["ShallowReactive",2],{"connector:cortex-debug-10:en":3},{"connector":4,"prose":78,"confirmations":82},{"schemaVersion":5,"governance":6,"meta":18,"pins":36},"1.0.0",{"publication":7,"verification":10,"provenance":15},{"status":8,"publishedDate":9},"published","2026-09-26",{"status":11,"verifiedDate":9,"verifiedBy":12,"checklist":13},"verified","Claude (LLM review against cited primary sources)",{"schema":14,"technicalFacts":14,"relationships":14,"sources":14},true,{"sourceUrls":16},[17],"https:\u002F\u002Fdocumentation-service.arm.com\u002Fstatic\u002F6347d0bdda191e7fe0580562",{"slug":19,"name":20,"title":21,"standard":22,"positionCount":23,"layout":24,"category":25,"source":26,"specs":32,"overview":34},"cortex-debug-10","ARM Cortex 10-Pin SWD Header","ARM Cortex 10-Pin 0.05-inch (1.27mm) Micro Debug & SWD Header","ARM CoreSight 10-pin",10,"dual-row","debug_swd",[27],{"label":28,"url":17,"authority":29,"documentType":30,"publisher":31},"Arm DSTREAM-PT System and Interface Design Reference Guide, Issue 03 (101714_1.0_03_en)","primary","manufacturer_documentation","Arm",{"standard":33,"positions":23},"ARM Cortex 10-Pin 1.27mm Pitch",{"summaryKey":35},"connectors.cortex10.summary",[37,42,47,52,56,58,62,68,72,75],{"n":38,"category":39,"signal":40,"role":41,"standardized":14},1,"power","VTREF","Target reference voltage: the probe matches its logic levels to it and detects the target when it exceeds 0.8 V",{"n":43,"category":44,"signal":45,"role":46,"standardized":14},2,"jtag","SWDIO \u002F TMS","Serial Wire debug data I\u002FO \u002F JTAG test mode select",{"n":48,"category":49,"signal":50,"role":51,"standardized":14},3,"gnd","GND","Ground",{"n":53,"category":44,"signal":54,"role":55,"standardized":14},4,"SWCLK \u002F TCK","Serial Wire clock \u002F JTAG test clock",{"n":57,"category":49,"signal":50,"role":51,"standardized":14},5,{"n":59,"category":44,"signal":60,"role":61,"standardized":14},6,"SWO \u002F TDO","Serial Wire trace output \u002F JTAG test data out",{"n":63,"category":64,"signal":65,"role":66,"standardized":67},7,"nc","KEY","Polarization key: no pin, not connected",false,{"n":69,"category":44,"signal":70,"role":71,"standardized":14},8,"TDI","JTAG test data in (unused in Serial Wire mode)",{"n":73,"category":49,"signal":50,"role":74,"standardized":14},9,"Ground; Keil documentation calls it GNDDetect, used by the probe to sense a connected target",{"n":23,"category":44,"signal":76,"role":77,"standardized":14},"nSRST","Target system reset, active low (nRESET in Keil documentation)",{"description":79,"card":80,"intro":81},"ARM Cortex 10-pin 1.27 mm debug header pinout: VTREF, SWDIO\u002FTMS, SWCLK\u002FTCK, SWO\u002FTDO, TDI, nRESET and grounds, checked against Arm probe documentation.","Compact 10-pin, 1.27 mm ARM Cortex SWD debug header.","The 10-pin Cortex debug header is the compact 1.27 mm connector for Serial Wire Debug and JTAG on Arm Cortex-M boards. Select a contact to see its SWD and JTAG function.",null,1791663948594]